1. Field of the Invention
The present invention relates to a semiconductor memory and an FBC memory cell driving method.
2. Related Art
Development of a floating body cell (FBC) memory is underway as a memory in place of a dynamic random-access memory (DRAM). Further, following scale-down of a size of an element, a double-gate full-depletion FBC (hereinafter, “FD-FBC”) memory has been developed. The FD-FBC memory includes a body region in a floating state formed in a semiconductor on insulator (SOI) substrate, a source layer on one side of said body region and a drain layer on another side of said body region, a front gate electrode provided on a gate insulating film formed on the body region, and a back gate electrode buried in a buried oxide (BOX) layer.
The FD-FBC memory is equal to a partial-depletion FBC (hereinafter, “PD-FBC”) memory in that data “1” or “0” can be stored by storing or emitting holes in this body region. The FD-FBC memory differs from the PD-FBC memory in the following respect. As for the PD-FBC memory, a factor that determines a threshold voltage of the body region is an impurity concentration of the body region. As for the FD-FBC memory, a factor that determines a threshold voltage of the body region is an influence of electric fields of the front gate electrode and the back gate electrode on a channel surface. In other words, in the FD-FBC memory, the back gate electrode is biased to a sufficiently negative potential to retain data. A potential well is thereby formed, and holes are stored in the body region. The FD-FBC memory does not, therefore, need to introduce impurities into the body region and the body region may consist of an intrinsic semiconductor. In the FD-FBC, a scale of an element can be scaled down while a threshold voltage difference ΔVth between data “1” and data “0” is kept large by making a thickness of the SOI layer small. Further, in the FD-FBC, a fluctuation in a threshold voltage of a memory cell resulting from an irregularity of impurity concentration in the body region can be reduced.
However, if the thickness of the SOI layer is made smaller as the element is smaller in size, a potential applied to the back gate electrode needs to be a high negative potential so as to keep a state in which the holes are stored in the body region (a state of data “1”). A field intensity between the back gate electrode and the body region is higher, accordingly. This field intensity acts to store holes in the body region in a state in which no hole is stored (a state of data “0”). As a result, a data retention related disadvantage occurs that a data “0” retaining capability is deteriorated. It is, therefore, desired to provide a semiconductor memory that can suppress a deterioration in a data retaining capability and that can be made sufficiently small in size.